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fn9146 rev 1.00 page 1 of 16 mar 2004 fn9146 rev 1.00 mar 2004 ISL6111 current regulated pci hot plug power switch controller datasheet the ISL6111 is designed for use in pci and pci-x applications where active current regulation protection of the motherboard from an abnormal pci load card is desired. with the addition of two discrete power mosfets and a few passive components, the ISL6111 provides power control for the four legacy supplies (-12v, +12v, +5v, +3.3v) to a pci or pci-x slot. this ic integrates the +12v and -12v current sensing and regulation switches. on the 25w capable 3.3v and 5v rails, current regulation (cr) protection is provided by sensing the voltage across external current-sense resistors and modulation of t he gate voltage bias on the external n-channel power mosfets. during initial power-up of the +12v bias supply, the enable (en), power good (pg), fault monitoring and reporting function functions are inhibi ted if bias voltage <10v. once the fets are enabled they are soft started into the load thus eliminating supply rail disturbances. upon a failure that quickly c auses a load current greater than the programmed cr level on any voltage supply, the ISL6111 enters its current regul ation (cr) mode , limiting the load current to the user pro grammed level for the user determined period of time. the cr level and duration are set by a single resistor and capacit or respectively. at the end of the cr duration all t he switches will lat ch off pulling the outputs low along with the crti m (current regulation timer) and fltn (fault not) pins indicating a latch-off due to an over current (oc) condition. if a se vere oc condition should occur, then the ISL6111 immediately latches off all outputs and sets the fltn output low. during operation, if any of the p ositive voltages falls below the minimum pci specified le vels the power good (pg) output will pull low indicating a non compliant voltage to a load. pg is an open drai n output as is fltn. the crset pin allows programming of the current regulation levels to be scal ed up or down from the pci specified levels via a resis tor connected between the crset pin and ground. all faults and latches are cleared by enable being deasserted low. features ? active current regulation for protection ? adjustable current regulation duration and magnitude ? internal mosfet switches fo r +12v and -12v outputs ? provides fault isolation ? adjustable turn-on slew rate ? minimum parts count solution ? no charge pump ? 1s response time to over current ? pb-free leadframe applications ?pci ? pci-x 1.0 pinout ISL6111 (5x5 qfn) top view ordering information part number temp. range (c) package pkg. dwg. # ISL6111crza (see note) 0 to 75 20 ld 5x5 qfn (pb-free) l20.5x5 ISL6111eval2 evaluation platform note: intersil lead-free products employ special lead-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which is compatible with bo th snpb and lead-free soldering operatio ns. intersil lead-free products are msl classified at lead-free peak reflow temperatures that meet or exceed the lead-free requirem ents of ipc/jedec j std-020b. m12vg gnd_a 12vo_b 12vo_a 5vg 3vg 12vi_a gnd_b 12vi_b pgood 3vs 3visen crset m12vo m12vi crtim fltn 5visen 5vs en 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 -12v o b s o l e t e p r o d u c t n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
ISL6111 fn9146 rev 1.00 page 2 of 16 mar 2004 typical application 12v, m12vin crtim 3vg 3visen 12vi(2) 3vs pg fltn m12vo 5vg gnd(2) 12vo(2) 5visen 5vs crset m12vg ISL6111 3.3v, 12v supply 5v, -12v, 5v supply -12v supply enable input 5nf 3.3v supply 7.6a out 0.5a out 0.1a out 5a out en faultn v(i/o) v(i/o) power good r crset c crtim notes: 1. see table 1 for cr level formula 2. see table 2 for cr duration vs c tim . figure 1. ISL6111 typical application schematic (note 1) (note 1) (note 1) (note 2) (note 1) r sense_5 r sense_3 (note 1) (note 1) (note 1)
ISL6111 fn9146 rev 1.00 page 3 of 16 mar 2004 simplified schematic faultn 5v s 5v g 5v isen 3v s crset 3v isen 12v in 12v o m12v in m12v g m12v o enable gnd 12v in power-on reset 12v in m12v in 12v in 12v in 100a 0.3 ? 0.7 ? fault v ocset 5v zener reference 12v in 5v ref 5v ref 4.6v 12v in reset 12v in low when 12v in < 10v high = switches on high = fault comp - + comp + 2.9v comp + - 10.6v comp + - comp - + + - 12v in 12v in - latch pgood + - woc comp - + - + amp comp - + + - 2.8v crtim 20a 12v in + - + - 12v in comp - + + - woc comp - + - + + - + - 3v g + - woc comp - + + - amp amp comp - + + - + - woc comp - + + - amp
ISL6111 fn9146 rev 1.00 page 4 of 16 mar 2004 pin descriptions pin no. designator function function description 1 3vg 3.3v fet gate output drives the gate of the 3.3v mosfet. con nect to the gate of the external n-channel mosfet. at turn-on the fet gate capacitance will be charged to 12vin voltage by a 10 ? a current source. an optional capacitor from this node to ground will adjust the turn-on ramp. 2, 4 12vi 12v input +12v ic bias s upply and power supply rail inpu t to internal power switch. 3, 14 gnd ic ground reference connect to common of power supplies. 5 pgood power good an open drain logic output that is released to indicate all positive voltage outputs are above minimum pci spec. connect to v (i/o) through resistor. 6 crtim current regulation duration input an external capacitor from this pin to ground sets the current regulation duration before latch off. this output will pull low after the current regulati on duration has expired. cr duration = 150k x ctim. this pi n sources 20a and has a thresho ld trip voltage of 2.83v. 7 fltn fault indication a fault-not open drain output. latches low once current regulation time has expired. reset by 12vin por condition or en able input signaled low. connect to v(i/o) through resistor. 8 5visen 5v current sense connect to the load side of the current sense resistor in series w ith source of external 5v mosfet. monitors voltage to load. 9 5vs 5v source connect to source of 5v mosfet switch. this connec tion along with 5visen senses the voltage drop across the sense resistor. 10 en enable input controls all four internal and external switche s, initiates turn-on/off 11 5vg 5v fet gate output drives the gate of the 5v mosfet. connec t to the gate of the external n-channel mosfet. at turn-on the fet gate capacitance will be charged to 12vin voltage by a 10 ? a current source. an optional capac itor from this node to ground will adjust the turn-on ramp 12, 13 12vo switched 12v output switched 12v output. 15 m12vg gate of internal nmos connect a 5nf capacitor between m12 vg and ground to stabilize the start-up ramp for the m12v supply. this capacitor is charged with 25 ? a during start-up. 16 m12vi -12v input -12v supply inpu t. also provides power to the -12v current regulation circuitry. 17 m12vo switched -12v output switched -12v output. 18 crset current regulation set program current regulation levels for all four switches by connecting a resistor to gnd. this pin sources 100a. see table 1 for cr level setting formulae. 19 3visen 3.3v current sense connect to the load side of the curre nt sense resistor in series with source of external 3.3v mosfet. monitors voltage to load. 20 3vs 3.3v source connect to source of 3.3v mosfet. this connect ion along with 3visen senses the voltage drop across the sense resistor.
ISL6111 fn9146 rev 1.00 page 5 of 16 mar 2004 absolute maximum ratings thermal information 12vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +15.0v 12vo, 3vg, 5vg . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 12vi+0.5v m12vi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0v to +0.5v m12vo, m12vg. . . . . . . . . . . . . . . . . . . . . . . v m12vi -0.5v to +0.5v 3visen, 5visen . . . . . . . . . . . -0.5v to the lesser of 12vi or +7.0v voltage, any other pin. . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8a esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kev (hbm) operating conditions 12vin supply voltage range . . . . . . . . . . . . . . . . +10.8 v to +13.2v 5v and 3.3v input supply tolerances ??????????????????????????????????????????? ? 10% 12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.5a m12vo output current . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +0.1a temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0c to 85c thermal resistance (typical, notes 3, 5) ? ja (c/w) ? jc (c/w) qfn package. . . . . . . . . . . . . . . . . . . . 31 2.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 3. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 4. all voltages are relative to gnd, unless otherwise specified. 5. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications nominal 5.0v and 3.3v input supply voltages, 12vi = 12v, m12vi = -12v, t a = t j = 0 to 75c, unless otherwise specified parameter symbol test conditions min typ max units 5v/3.3v current control 5v current regulation threshold voltage v oc5v v crset = 0.3v - 26.5 - mv 5v woc threshold voltage v oc5v_woc v crset = 0.3v 49 - mv 5v current regulation level i cr5v_3 r crset = 3k (see figure 1, typical application) - 5.3 - a i cr5v_35 r crset = 3.5k (see figure 1, typical application) - 5.8 - a i cr5v_4 r crset = 4k (see figure 1, typical application) - 6.4 - a i cr5v_46 r crset = 4.64k (see figure 1, typical application) - 7.2 - a slow ramping current trip level ct/cr di/dt = 0.001a/s, current t rip level/current regulation level -90-% current trip level temp coeff. ct_t dct/85c (see figure 1, typic al application) - 3.5 - ma/c 5v undervoltage threshold v 5vuv 4.51 4.57 4.64 v 5v turn-on time (en to 5vout = 4.5v) t on5v c 5vout = 3300 ? f, r l = 1 ?? v crset = 0.35v ? -7-ms 5v turn-off time (en to 5vout = 0.5v) t off5v c 5vout = 3300 ? f, r l = 1 ?? v crset = 0.35v ? -6-ms 3.3v current regulation threshold voltage v oc3v v crset = 0.3v - 39.5 - mv 3.3v woc threshold voltage v oc3v_woc v crset = 0.3v - 80 - mv 3.3v current regulation level i cr3v_3 r crset = 3k (see figure 1, typical application) - 7.9 - a i cr3v_35 r crset = 3.5k (see figure 1, typical application) - 8.7 - a i cr3v_4 r crset = 4k (see figure 1, typical application) - 9.8 - a i cr3v_46 r crset = 4.64k (see figure 1, typical application) - 10.9 - a slow ramping current trip level ct/cr di/dt = 0.001a/s, current t rip level/current regulation level -90-%
ISL6111 fn9146 rev 1.00 page 6 of 16 mar 2004 current trip level temp coeff. ct_t dct/85c (see figure 1, typic al application) - 3.5 - ma/c 3.3v undervoltage threshold v 3vuv 2.7 2.8 2.9 v 3.3v turn-on time (en to 3vout = 3v) t on3v c 3vout = 3300 ? f, r l = 0.5 ??? v crset = 0.35v ? -6-ms 3.3v turn-off time (en to 3vout = 3v) t off3v c 3vout = 3300 ? f, r l = 0.5 ??? v crset = 0.35v ? -5-ms current limit amp offset voltage vio_ft vs - visen -6 0 6 mv current limit amp offset voltage vio_pt vs - visen, t j = 15c to 55c -2 0 2 mv external gate drive response time to oc pd_oc_amp v gate to 11v - 100 - ns response time to oc pd_oc_gate_10 v gate to 10v - 10 - ? s turn-off time to woc pd_woc_amp v gate to 2v - 1 - ? s turn-on current i gate v gate to = 6v 8 10 12 ? a turn-on time (en to vg = 1v) t ongate 3vg, 5vg rising to 1v - 400 - ? s pull down current oc_gate_i_4v overcurrent 20 35 50 ma woc pull down current woc_gate_i_4v severe overcurrent 0.5 0.8 1.5 a high voltage vg_high gate on voltage vdd-1v vdd - v low voltage vg_low gate off voltage - 0.5 0.7 v +12v supply control on resistance of internal pmos @ 0.5a r ds(on)12 t a = t j = 25c - 0.3 - ? t a = t j = 85c - 0.35 - ? current regulation level i cr12v v crset = 0.3v 0.45 0.52 0.55 a i cr12v_35 r crset = 3.5k - 0.54 - a i cr12v_4 r crset = 4.0k - 0.56 - a i cr12v_45 r crset = 4.64k - 0.62 - a slow ramping current trip level ct/cr di/dt = 0.001a/s, current t rip level/current regulation level -80-% current trip level temp coeff. 12vct_t dct/85c - 0.6 - ma/c 12v undervoltage threshold v 12vuv 10.57 10.7 10.9 v vout turn-on time t on12v 12v rising 10% - 90%, c 12vo = 50 ? f, r l = 25 ? -1.7-ms vout turn-on time t on12v 12v rising 10% - 90%, c 12vo = 300 ? f, r l = 25 ? -5-ms vout turn-off time t off12v 12v falling 90% - 10%, c 12vo = 300 ? f, r l = 25 ? -15-ms vout turn-off time woc t off12vwoc 12v falling 90% - 10%, c 12vo = 300 ? f, r l = 25 ? -35- ? s vout turn-off voltage v off12 vout when off - 0.3 - v -12v supply control on resistance of internal nmos @ 0.1a r ds(on)m12 t a = t j = 25c - 0.7 - ? t a = t j = 85c - 0.9 - ? current regulation level i cmr12v v crset = 0.3v 0.085 0.11 0.135 a i cmr12v_35 r crset = 3.5k - 0.115 - a i cmr12v_4 r crset = 4.0k - 0.120 - a i cmr12v_45 r crset = 4.64k - 0.140 - a electrical specifications nominal 5.0v and 3.3v input supply voltages, 12vi = 12v, m12vi = -12v, t a = t j = 0 to 75c, unless otherwise specified (continued) parameter symbol test conditions min typ max units
ISL6111 fn9146 rev 1.00 page 7 of 16 mar 2004 slow ramping current trip level ct/cr di/dt = 0.001a/s, current t rip level/current regulation level -90-% current trip level temp coeff. m12vct_t dct/85c - 0.1 - ma/c gate turn-off time t offm12vg c m12vg = 0.005 ? f, m12vg falling 90% to 10% - 330 - ns gate response time to overcurrent t oc2m12vg -11 ? s gate response time to woc t woc2m12vg - 400 - ns gate output charge current ic m12vg enable = high, v m12vg = -10v - 102 - ? a vout turn-on time t onm12vo -12v falling 90% - 10%, c m12vo = 50 ? f, r l = 120 ? -11-ms vout turn-on time t onm12vo -12v falling 90% - 10%, c m12vo = 150 ? f, r l =120 ? -35-ms vout turn-off time t offm12vo -12v rising 10% - 90%, c m12vo = 150 ? f, r l = 120 ? -40-ms vout turn-off time woc t offm12vowoc -12v rising 10% - 90%, c m12vo = 150 ? f, r l = 120 ? -15- ? s vout turn-off voltage v offm12vo vout when off - -0.6 - v m12vin input bias current ib m12vin enable = high 4.5 5.3 7 ma control and i/o pins crset current source i crset 90 100 110 ? a rising enable threshold voltage v th_en_l2h 1.5 1.7 2.0 v falling enable threshold voltage v th_en_h2l 1.2 1.5 1.9 v enable threshold voltage hysteresis v th_en_hys -0.20.3v enable to output turn-on prop. del ay tpd_en enable high to start of output turn=on - 2 - ms power good output low voltage v pg,l i pg = 5ma - 0.6 0.75 v power good output pull-down current i pg -40-ma power good to vout falling response time t uv2pg_fall vout < uv vth to pg low - 500 - ns power good to vout rising response time t uv2pg_rise vout >uv vth to pg high - 8 - ms faultn output low voltage v fltn,l i fltn = 5ma - 0.6 0.75 v faultn output pull-down current i fltn -40-ma faultn output response time t oc2fltn c tim _vth to fltn low - - 1 s crtim charging current crtim_ichg0 v ctim = 0v - 26 - ? a current regulation time-out threshold crtim_vth ctim voltage 2.7 4 2.83 2.92 v bias 12v lock out threshold v por,thrise v cc voltage rising 9.88 10.1 10.5 v 12v power on reset threshold v por,thfall v cc voltage falling 9.17 9.3 9.43 v 12v reset threshold hysteresis v por,hys -0.69- v 12v disabled supply current i dis 12vin, en = 0v - 3.3 6 ma electrical specifications nominal 5.0v and 3.3v input supply voltages, 12vi = 12v, m12vi = -12v, t a = t j = 0 to 75c, unless otherwise specified (continued) parameter symbol test conditions min typ max units
ISL6111 fn9146 rev 1.00 page 8 of 16 mar 2004 introduction the ISL6111, is an ic device de signed to provide control and protection of the four legacy pci power supplies (+12v, -12v, +5v and +3.3v) for a single p ci or pci-x slot. unlike the widely used hip1011, this devi ce employs an a ctive current regulation (cr) method to provi de system prote ction against load faults. figure 1 illustrates the typical implementation of the ISL6111. key feature description and operation the ISL6111, 2 power mos fets and a few passive components as configured in f igure 1, completes a power control solution for the legacy supplies to a pci slot. it prov ides protection via a programmable maximum current regulation (cr) level to the load for each supply. for the 3.3v and 5v supplies, current monitoring is provided by sensing the voltage across external current-sense r esistors, and cr protection is provided by active vo ltage modulation of external n-channel mosfets. for the +12v and -12v supplies, current monitoring and cr protection are provided internally. during initial power-up of the main bias supply pins (12vi), th e enable input function is inhibited from turning on the switches, this latch is held in the reset state until the bias voltage is greater than 10v ( por rising). additionally the power good and fault reporting func tions are also disabled at this time and during the soft start duration. during turn-on of the supplies on to their capacitive loads the current limiting fail-safe is engaged, this limited current giv es a voltage ramp-up slew rate cente red within the pci specs. as the startup is current-limit ed, the crtim timer is engaged during the entire startup, as it should be. this eliminates the otherwise destructive case of s tarting up into a dead short. depending on loading, the positive 3 supplies will start up and exit current limiting in abou t 6ms -10ms. the -12v supply will take much longer, as it has a fr action of the available chargin g current into a potentially relatively very large load capacitan ce, and the voltage has to slew to -12v. the -12v turn-on duration can thus be several times as l ong extending to ~50ms for a very capacitive (147f) load in conjunction with a maximum current load. in addition if the c r level is too low then its possible that the load capacita nce cannot fully charge in the allowed for time, this is the consequence of the current regulation limiting protection. once turned on, any subsequent over current (oc) condition on any output results in the affected switch (external or internal) to be put into its lin ear mode of operation, and the current is regulated to the leve l determined by t he choice of external crset resistor value . an oc condition is defined as a current level > the programmed cr level and that transitions through the cr level with a quick ramp, <0. 5s. this cr level is maintained until the oc condition passes or the cr duration expires, whichever comes fir st. the cr duration is user defined by the capacitor value o n the crtim pin. once in cr mode, the crtim pin charges the capacitor with a 20a current until the voltage on crti m rises to ~2.8v, at which tim e a turn-off latch is set on all 4 power fet switch es. also at th is time the open drain fault (fltn) output is pulled low signallin g a latched off state. after a fau lt has been asserted and fltn i s latched low, cycling enable lo w will clear the fltn latch. on-chip references in the ISL6111 are used to monitor the +5v, +3.3v and +12v outputs for und er voltage (uv) conditions. once an uv condition is present the open drain power good (pgood) output will pull low to indicate this. customizing circuit performance setting current regulation (cr) level the ISL6111 allows for easy and simultaneous custom programming of the cr levels of all 4 supplies by simply changing the resistor value between crset, (pin 18), and ground. the r crset value and the crset 100 ? a current source create a reference volta ge that is used in each of four comparators. the ir voltages developed across the 3.3v and 5v sense resistors are applied to the inputs of their respectiv e comparators opposite this ref erence voltage. the +12v and - 12v currents are sensed internally with pilot devices. because of the internal current monitoring of the +12v and -12v switches, their programming f lexibility is limited to r crset changes whereas the 3.3v and 5v over current regulation levels depend on both r crset , and the value chosen for each sense resistor. see table 1 to deter mine cr protection l evels relative to choice of r crset and r sense values. over current design guidelines and recommendations are as follows: 1. for pci applications, set r crset to 4.22k ? , and use 5m ? 1% sense resistors (s ee figure 20). this r crset value provides a nominal current tri p level 110% to 130% higher than the maximum specified cu rrent, to ensure full current range use by the pci load. t he ISL6111 will trip off on a slow increasing current ramp approximately 10% to 20% lower than set cr level. 2. for non pci specified applications, the following precautions and limitations apply: a. do not exceed the maximum power of the integrated nmos and pmos. high power dissipation must be coupled with effective thermal management and prudent cr durations. the integrated pmos has an r ds(on) of 0.35 ? . with 2.5a of steady load cu rrent on the pmos device the power dissipation is 2.2w. the thermal impedance of the package is 31 degrees celsius per watt, resulting in a 68c die temp rise thus limiting the average dc current on the 12v supply to about 2.5a maximum at +85c ambient and imposing an upper limit on the r ocset resistor. do not use an r crset resistor greater than 15k ? . the average current on the - 12v supply should not exceed 0.8a. since the thermal restrict ions on the +12v supply are more severe, the +12v supply restricts the use of the ISL6111 to applications where the ? 12v supplies draw
ISL6111 fn9146 rev 1.00 page 9 of 16 mar 2004 relatively little current. since both supplies only have one degree of freedom, the value of r ocset , the flexibility of programming is quite limited. f or applications where more power is required on the +12v supply, contact your local intersil sales representative for information on other hot plug solutions. b. do not try to sense voltages acr oss the external sense resistors that are less than 2 0mv as spurious faults due to noise and comparator input sen sitivity may result. the minimum recommended r crset value is 3.0k ? . this will set the nominal oc voltage thresholds at 39mv and 26mv for the 3.3v and 5v comparators respectively. c. minimize v rsense so as to not significantly reduce the voltage delivered to the ad apter card. remember pcb trace and connector distribution voltage losses also need to be considered. make sure that the r sense resistor can adequately handle the dissipated power. for best results use a 1% precision resistor with a low temperature coefficient. d. minimize external fet r ds(on) . low r ds(on) or multiple mosfets in parallel are recommended. current regulation dela y time to latch-off the cr time delay to latch-off , allows for a predetermined delay from the start of cr, to the simultaneous latch-off of al l four supply switches to the load. this delay period is set by t he capacitor value to ground from the crtim pin. this feature allows the ISL6111 to provide a current regulated soft start in to all loads, and to delay immediate latch-off of the bus supply switches thus ignoring transient oc conditions. see table 2. for cr duration vs crtim capacitance value. caution: an additional concern about long cr durations along with mb supply droop is power-fet survivability. the primary purpose of a protection devic e such as the ISL6111 is to quickly isolate a faulted card from the voltage bus. delaying the time to latch-off works agai nst this primary concern so understand the limitations and re alities. since we use the same crtim cap timing cap for all sup plies, we have to set that cap to a size large enough to allow the -12v t o start up under the worst load for a given system. if we set this t o a 75ms duratio n, then this 75ms time-out duration will also be used when one of the higher power supplies goes into current limiting after startup is complete. the highest power supplies, the 3.3v and 5v each run to a maximum of 25w, as allowed by the pci spec. if our overcurrent dur ation is set to 75ms, then theoretically (but extremely un likely) more than 25w can be dissipated in the external fet for that whole duration. the ISL6111 has a way over-current " woc" circuit that faults the chip off instantly if this theo retical dead short happens so quickly that the current limiting circuitry can't keep up. in r eality, overcurrent is more likely to n ot be a zero-ohm short, and only a fraction of the power is dissipated in the fet. ensure adequate sizing of external fets to carry additional current during cr perio d in linear operation. by looking at the soa of the siliconix si4404dy fet and even presupposing the full 25w for 100ms duration for a single pulse is not an issue with this power fet. this fet is representative of fets for a pci application. if for a higher power non pci design, consult the mosfet vendor soa curves. application considerations soft start and turn-off considerations the ISL6111 does allow the user to select the rate of ramp up on the voltage supplie s. this start-up ram p minimizes in-rush current at start-up whi le the on card bulk capacitors charge. the ramp is created by placing capacitors on m12vg, 3vg and 5vg to ground. these capacit ors are each ch arged up by a nominal 25 ? a current during turn on . the +12vo has internal current controlled ramping circuitry. the same value for all ga te timing capacitors is recommended. the gate capacitors must be discharged when a fault is detected to turn off the power fets thus, larger caps slow t he response time. if the gate capacitors are too large the ISL6111 may not be able to adequately protect the bus or th e power fets. the ISL6111 has internal discharge fets t o discharge the load when disabled. upon turn-off these in ternal switches on each output discharge the load capacitan ce pulling the output to gnd. these switches are also on when enable is low thus an open slot is held at the gnd level. recommended pcb layout design to ensure accurate current s ensing and cont rol, the pcb traces that connect each of the current sense resistors to the ISL6111 must not carry any load current. this can be accomplished by two dedicated pcb kelvin traces directly from the sense resistors to the ISL6111, see examples of correct and incorrect layouts below in fi gure 2. to reduce parasitic table 1. supply nominal current regulation level (10%) for each supply +3.3v i cr ((100 ? a x r crset )/8.54)/r rsense +5.0v i cr ((100 ? a x r crset )/12)/r rsense +12v i cr (100 ? a x r crset )/0.7 -12v i cr (100 ? a x r crset )/3.3 table 2. crtim, value 0.022f 0.1 ? f1 ? f nominal cr duration 3.3ms 15ms 150ms nominal cr duration = 150k ? x tim cap value.
ISL6111 fn9146 rev 1.00 page 10 of 16 mar 2004 inductance and resistance effects, maximize the width of the high-current pcb traces. pgood vs power is good and fault signals keep in mind that the -12vou t is not monitored for under voltage, thus the pgood output signal only takes into account the three positive supplies. p good will assert once all minimum positive uv criteria is reached and the m12vo may not be more than a fe w volts below ground at that time. it will pull low once any positive volt age < uv vth. for applications that don't use -12v, the m12vi pin on the ISL6111 is simply grounded. the fault-not output, fltn pulls low once the cr duration has expired and signals that all supplies have been disconnected from the load. s ee figure 3 for operational pgood and fltn waveforms. adjusting the current regulation level the current regulation leve l is adjusted by the crset resistance to ground value. t he ratio of resistance to cr change is not linear but is unidirectional in relationship, see figures 4-6. correct to ISL6111 vs and visen to ISL6111 vs and visen current sense resistor incorrect figure 2. sense resistor pcb layout figure 3. fltn & pgood functional waveform 20ms/div 5vout 2/div 5iout 5a/div cr = 7.2a crtim 2v/div pgood / fltn 5/div typical performance curves & waveforms figure 4. 3.3v & 5v slowly increasing current trip level vs temperature and rcrset figure 5. +12v & -12v slowly increasing current trip level vs temperature and rcrset 0 2 4 6 8 10 12 33.544.5 r_crset (k ? ) amps 5v 3.3v 0c 85c 25c 0 0.1 0.2 0.3 0.4 0.5 0.6 33.544.5 r_crset (k ? ) amps +12v -12v 25c 0c 85c
ISL6111 fn9146 rev 1.00 page 11 of 16 mar 2004 figure 6. nominal current trip level vs rcrset figure 7. r on vs temperature figure 8. 12v uv vth vs temperature figure 9. uv trip vs temperatu re figure 10. bias current vs temperature figure 11. 12v enable and r eset threshold voltages vs temperature typical performance curves & waveforms (continued) 13 11 9 7 5 3.3v, 5v current trip level (a) 3.0k 3.5k 4.0k 4.5k 12v, -12v current trip level (a) 0.55 0.425 0.3 0.175 0.05 3.3v 5v 12v -12v 450 437 375 337 300 1200 1100 1000 900 800 pmos r on +12 (m ? ) nmos r on -12 (m ? ) temperature (c) 025507585 pmos +12 r on nmos -12 r on 10.75 10.732 10.716 10.70 025507585 12 uv trip (v) temperature (c) 4.59 4.58 4.57 5v uvtrip (v) 3.3v uvtrip (v) temperature (c) 5 uv 2.9 2.85 2.8 3.3 uv 025507585 6 5 4 3 abs 12v bias (ma) temperature (c) 025507585 10.0 9.66 9.33 9.0 +12v thresholds (v) temperature (c) 025507585 +12v por_rising +12v por_falling
ISL6111 fn9146 rev 1.00 page 12 of 16 mar 2004 using the ISL6111eval2 platform biasing and general information the ISL6111eval2 platform (figur e 20) allows a designer to evaluate and modify the perform ance and functionality of the ISL6111 in a simple environment . the board is made such that the heat dissipating resistors are shiel ded from u sers and equipment by being placed on the bottom, despite this the top o f the load board still gets hot. test point names correspond to th e ISL6111 device (u1) pins. along with the ISL6111 on the is l6111eval2 platform are 2 n- channel power mosfets, (q1- q2 ) these are used as the external switches for the +5v an d +3.3v supplies to the load. current sensing is facilitated by the two 5m ? 1w metal strip resistors (r7, r3), the volt ages developed across the sense resistors are compared to references on board the ISL6111. the ISL6111eval2 platform is powered through the 5 labeled jacks on the left half of the b oard, with outputs on the right half. after properly biasi ng the ISL6111, signal the enable input high (>2.4v), this will turn on the fet switches and apply voltage to the loads resistors and capacitors. voltage and current measurement s can be easily made as the test points facilitate access to ic pins and other critical cir cuit nodes. evaluating current regulation duration the current regulation (cr) duration is set by the crtim capacitor value, c3 to ground. this provides a programmable duration during which the is l6111 holds the programmed cr level. once this duration has expired and the ISL6111 is still in cr mode the output voltages will turn off. the intent of any protection dev ice is to quickly isolate the voltage supplies so a faulty load card does not drag down a supply. a duration period too l engthy increases the likelihood of fet switch damage and results in slower isolation of the faulty card from the rest of system. figures 14 -19 s how nominal turn-on, turn -on into oc condition with cr mode waveforms. figure 12. crset current vs temperature figure 13. crtim threshold voltage vs temperature typical performance curves & waveforms (continued) 101 100 99 98 97 ioc set (a) temperature (c) 025507585 2.74 2.72 2.70 2.68 temperature (c) crtim latch off threshold (v) 025507585
ISL6111 fn9146 rev 1.00 page 13 of 16 mar 2004 typical performance curves figure 14. ISL6111 turn-on into nominal load figure 15. ISL6111 tu rn-on into m12v oc condition figure 16. m12vout into cr (vcrset = 0.461v) figure 17. 12vout int o cr (vcrset = 0.461v) figure 18. 3.3v into cr (vcrset = 0.461v) figure 19. 5vout into cr (vcrset = 0.461v) +5vout 5v/div en 10v/div ctim 1v/div 4ms/div 12vout 5v/div +3.3vout 5v/div m12vout 5v/div en 10v/div 12vout 5v/div +5vout 5v/div +3.3vout 5v/div ctim 1v/div -12vout 5v/div 10ms/div 12vout 5v/div tim 5v/div m12iout 0.1a/div cr = 0.12a 10ms/div 12iout 0.2a/div cr = 0.54a tim 5v/div 12vout 5v/div 10ms/div 10ms/div 3vout 1/div 3.3iout 5a/div cr = 10.2a 3vg 2v/div tim 5v/div 3vsupply 1/div 10ms/div 5vout 2/div 5iout 5a/div cr = 7.2a 5vg 2v/div tim 5v/div 5vsupply 2/div
ISL6111 fn9146 rev 1.00 page 14 of 16 mar 2004 figure 20. ISL6111eval2 platform schematic and photograph
fn9146 rev 1.00 page 15 of 16 mar 2004 ISL6111 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. table 3. ISL6111eval2 board component listing component designator component name component description controller board u1 ISL6111cr pci hotplug controller intersil, ISL6111cr pci hotpl ug controller q1, q2 siliconix si4404dy 4.5m ? , 30v, 23a logic level n-channel mosfet or equivalent r3, r7 sense resistor for 3.3v and 5v supplies wsl-2512 5m ? , 1% metal strip resistor or equivalent r5 current regulation set resistor 4.53k ? 0805 chip resistor c3 current regulation duration set capacitor 0.47f 0805 chip cap acitor (cr duration ~70ms) r1, r4 pgood , fltn pull-up resistor 5k ? 0402 chip resistor c1 12vi decoupling capacitor 1f 0603 chip capacitor c6 m12vg decoupling capacitor 5600pf 0402 chip capacitor c2, c5 optional gate timing capacitors not populated 0805 chip ca pacitor r2, r6 3.3v load resistor 2.2 ? , 5w r9, r10 5.0v load resistor 5.1 ? , 5w r11 +12v load resistor 47 ? , 5w r8 -12v load resistor 240 ? , 2w c4, c8 +3.3v and +5.0v load capacitors 2200f c9 +12v load capacitor 330f c7 -12v load capacitor 100f
ISL6111 fn9146 rev 1.00 page 16 of 16 mar 2004 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l20.5x5 20 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n202 nd 5 3 ne 5 3 p- -0.609 ? --129 rev. 3 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provid ed to assist with pcb land patte rn design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of t he package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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